(a) Field of the Invention
The present invention relates to a thin film transistor array panel, and in particular, to a thin film transistor array panel including a fan out area provided with a connection connecting a signal line to a pad and located between a display area and a pad area.
(b) Description of the Related Art
Generally, a thin film transistor (xe2x80x9cTFTxe2x80x9d) array panel for a liquid crystal display (xe2x80x9cLCDxe2x80x9d) or an electro-luminescence (xe2x80x9cELxe2x80x9d) display is used as a circuit board for driving respective pixels in an independent manner. The TFT array panel includes a scanning signal wire or a gate wire transmitting scanning signals, an image signal wire or a data wire transmitting image signals, TFTs connected to the gate and the data wire, pixel electrodes connected to the TFTs, a gate insulating layer covering the gate wire for insulation, and a passivation layer covering the TFTs and the data wire for insulation. The TFT includes a gate electrode, which is a part of the gate wire, a semiconductor layer forming a channel, source and drain electrodes, which are parts of the data wire, a gate insulating layer, and a passivation layer. The TFT is a switching element for transmitting the image signals from the data wire to the pixel electrode in response to the scanning signals from the gate wire.
A plurality of driving integrated circuits (xe2x80x9cICsxe2x80x9d) are connected to the TFT array panel for applying driving signals to the gate lines and the data lines. The driving ICs are connected to the gate lines or the data lines via pads, which are clustered on a narrow area for connection to the driving ICs. On the contrary, the distances between the gate lines or the data lines on a display area are determined by the size of the pixels to have larger values than the distances between the pads. Accordingly, a fan-out area where the distances between the signal lines gradually increase is provided between the pad area and the display area. The fan-out area results in the difference in the length between the signal lines, thereby causing different RC delays between the signal lines. The difference in the RC delay causes a difference in image signals resulting in a deteriorated image quality.
In accordance with the present invention, a difference in RC delay between signal lines of a thin film transistor array panel is reduced. A conductor having a varying width depending on an overlapping length of the conductor with signal lines is provided.
According to an embodiment of the present invention, a thin film transistor array panel is provided, which includes: an insulating substrate; a plurality of gate lines formed on the insulating substrate, each gate line including a pad for connection to an external device; a plurality of data lines intersecting the gate lines and insulated from the gate lines, each data line including a pad for connection to an external device; and a conductor overlapping at least one of the gate lines and the data lines, wherein an overlapping distance of the gate lines or the data lines and a width of the conductor decreases as the length of the gate lines or the data lines increases.
Preferably, each data line includes a pad portion including the pad, a display portion, and a fan-out portion connecting the display portion and the pad portion, and width of the fan-out portion of the data line increases as length of the fan-out portion of the data line increases. Preferably, each gate line comprises a pad portion including the pad, a display portion, and a fan-out portion connecting the display portion and the pad portion, and width of the fan-out portion of the gate line increases as length of the fan-out portion of the data line increases. The conductor is preferably applied with a common electrode voltage. It is preferable that the thin film transistor array panel further includes a pixel electrode located on a pixel area defined by intersections of the gate lines and the data lines, wherein the conductor includes substantially the same layer and the same material as the pixel electrode.
The conductor may overlap the gate lines, wherein the conductor includes substantially the same layer and the same material as the data lines. The conductor may overlap the data lines, wherein the conductor includes substantially the same layer and the same material as the gate lines. The conductor may include a first conductive segment overlapping the gate lines and a second conductive segment overlapping the data lines, the first conductive segment includes substantially the same layer and the same material as the data lines, and the second conductive segment substantially the same layer and the same material as the gate lines. The conductor may be floated.
According to another embodiment of the present invention, a thin film transistor array panel is provided, which includes: an insulating substrate; a plurality of gate lines formed on the insulating substrate, each gate line including a pad for connection to an external device; a gate insulating layer formed on the gate lines; a plurality of data lines formed on the gate insulating layer and intersecting the gate lines, each data line including a pad for connection to an external device; a passivation layer formed on the data lines; and a conductor overlapping at least one of the gate lines and the data lines via at least one of the gate insulating layer and the passivation layer.
It is preferable that an overlapping distance of the gate lines or the data lines and a width of the conductor decreases as the length of the gate lines or the data lines increases. Preferably, RC delays of the gate lines are substantially the same as each other, and RC delays of the data lines are substantially the same as each other.